Fault models for analog-to-digital converters

The author studies the fault models of an analog-to-digital converter (ADC) and relies on defect statistics (C. Stapper, 1985 and W. Maly et al., 1984) to derive the models according to the following procedure: collection of applicable manufacturing defect statistics for integrated circuits; mapping these statistics onto various layouts of the ADC circuits; defect analysis and fault derivation; and fault simulation. The author presents results of the ADC fault model study and discusses guidelines for test generation of mixed-signal communication circuits which employ the ADC in their designs. The results from a case study are compared. Preliminary results from this study are presented for two fault classes: opamp faults and MOS and capacitor faults