A parallel processor architecture for real-time digital image processing

Author

Sim, C.C. ; Wong, W.C. ; Ong, K.

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore

fYear

1992

fDate

16-20 Nov 1992

Firstpage

20

Abstract

The authors describe a parallel processor architecture for real-time digital image processing. The processors used are the AT&T WE DSP16A digital signal processors. The system designed consists of multiple DSP16As, and is constructed to perform computations in parallel. The completed hardware system has five DSP16As, and it is expandable to eight. The system uses a customized frame-grabber for image acquisition and display. It is specially tailored to suit the design of the multiple DSP hardware system. The system uses an IBM PC/AT, or compatible as the host. There are two communication paths between the system and the PC. The first uses memory mapped I/O for downloading DSP programs from the PC, and the other for full duplex data and command communication between the DSP and PC during run time

Keywords

IBM computers; digital signal processing chips; image processing equipment; microcomputer applications; parallel architectures; real-time systems; AT&T WE DSP16A digital signal processors; IBM PC/AT; command communication; customized frame-grabber; duplex data; image acquisition; image display; memory mapped I/O; parallel processor architecture; real-time digital image processing; Circuits; Digital images; Digital signal processing; Digital signal processors; Displays; Hardware; Image segmentation; Process design; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Singapore ICCS/ISITA '92. 'Communications on the Move'

Print_ISBN

0-7803-0803-4

Type

conf

DOI

10.1109/ICCS.1992.254949

Filename

254949