• DocumentCode
    3430638
  • Title

    A multiple-level heterogeneous architecture for image understanding

  • Author

    Shu, D.B. ; Nash, J.G. ; Weems, C.C.

  • Author_Institution
    Hughes Res. Lab., Malibu, CA, USA
  • fYear
    1990
  • fDate
    5-7 Sep 1990
  • Firstpage
    615
  • Lastpage
    627
  • Abstract
    The image understanding architecture (IUA) system is designed specifically for computer vision processing that relies heavily on artificial intelligence techniques to classify objects. To provide for low-, intermediate-, and high-level computer vision processing, the IUA system combines three heterogeneous levels of parallelism with associative processing mechanisms. The lowest level of the IUA contains a SIMD array of per pixel bit-serial processing elements with networking capabilities that exceed those of present bit-serial machines. The SIMD level is closely mated with a middle-level MIMD array of high-performance digital signal processing chips that communicate via a flexible, modular message-passing network. The dual-capability architecture is much more effective than a solely SIMD or MIMD organization. The highest level comprises an array of general-purpose microprocessors for symbol manipulation. The first- and second-generation implementations of the IUA architecture are described
  • Keywords
    artificial intelligence; computer vision; digital signal processing chips; parallel architectures; IUA architecture; SIMD array; artificial intelligence techniques; computer vision processing; digital signal processing chips; image understanding; middle-level MIMD array; modular message-passing network; multiple-level heterogeneous architecture; networking capabilities; parallelism; per pixel bit-serial processing elements; symbol manipulation; Application software; Artificial intelligence; Computer architecture; Computer vision; Digital signal processing chips; Intelligent sensors; Laboratories; Parallel processing; Sensor arrays; Sensor systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Array Processors, 1990. Proceedings of the International Conference on
  • Conference_Location
    Princeton, NJ
  • Print_ISBN
    0-8186-9089-5
  • Type

    conf

  • DOI
    10.1109/ASAP.1990.145497
  • Filename
    145497