DocumentCode
3430661
Title
An all-N-logic high-speed single-phase dynamic CMOS logic
Author
Gu, R.X. ; Elmasry, M.I.
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume
4
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
7
Abstract
In this paper, a new all-N-logic high speed pipelined single-phase dynamic CMOS logic is introduced and analysed. The use of an all-N-logic allows the speed of the proposed circuits to be 2-3 times the speed of conventional CMOS dynamic circuits. The operating speed of the proposed pipelined circuits is simulated using 0.8 μm CMOS technology and reaches as high as 890 MHz. The pipelined 8-b carry generator of 5-stacked NMOS´s which operates at a clock rate of over 550 MHz has been simulated
Keywords
CMOS logic circuits; carry logic; circuit optimisation; clocks; logic testing; pipeline processing; 0.8 micron; 550 to 890 MHz; 8 bit; all-N-logic; carry generator; clock rate; high speed pipelined circuit; operating speed; single-phase dynamic CMOS logic; stacked NMOS; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Clocks; Energy consumption; Frequency; MOS devices; Pipelines; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409183
Filename
409183
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