An arbitration discipline for buffered multistage interconnection networks

According to CCITT, ATM (asynchronous transfer mode) technology, based on packet switching, is chosen as the most promising technique to support the requirements of the future broadband networks. Internal communication is often one of the main obstacles to increasing performance of high speed packet switches (i.e., ATM switches). Parallel communication between packet processing devices attached to each communication line is a fundamental aspect of a new generation of broadband switches. The author presents the results that identify the effects of using buffered multistage interconnection networks (MINs) as the internal communications subsystems and discusses a new design for the arbitration logic of switching elements that leads towards higher performance of a broadband switch. It is shown that the arbitration discipline that removes the head of line (HOL) effect significantly improves the performance of switching elements, as well as MINs, if uniform traffic distributions are applied at the element input ports