Application-specific coprocessor computer architecture

Author

Chu, Yaohan

Author_Institution

Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA

fYear

1990

fDate

5-7 Sep 1990

Firstpage

653

Lastpage

664

Abstract

The coprocessor computer architecture has a main processor and one or more coprocessors. The author proposes the use of the coprocessor computer architecture for realizing high-performance, application-specific parallel computers. The author presents a classification of coprocessor computer organization. Matching a coprocessor computer organization with a parallel algorithm is suggested. As an example, a lexical/parsing coprocessor, which can deliver tokens from lexical processing at the rate of one million per second and semantic-rule codes from parsing at the rate of 2.5 million per second is described. This coprocessor shortens compilation time, reduces compiler size, and lessens programmer effort. This result clearly shows the potential use of the coprocessor computer architecture for application-specific computers

Keywords

application specific integrated circuits; digital signal processing chips; parallel algorithms; parallel architectures; application-specific parallel computers; compilation time; compiler size; coprocessor computer architecture; lexical/parsing coprocessor; parallel algorithm; programmer effort; semantic-rule codes; Application software; Computer applications; Computer architecture; Computer graphics; Concurrent computing; Coprocessors; Floating-point arithmetic; Hardware; Microprocessors; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Array Processors, 1990. Proceedings of the International Conference on

Conference_Location

Princeton, NJ

Print_ISBN

0-8186-9089-5

Type

conf

DOI

10.1109/ASAP.1990.145500

Filename

145500