• DocumentCode
    3430726
  • Title

    A four-channel self-calibrating high-resolution time to digital converter

  • Author

    Mota, M. ; Christiansen, J.

  • Author_Institution
    CERN, Geneva, Switzerland
  • Volume
    1
  • fYear
    1998
  • fDate
    1998
  • Firstpage
    409
  • Abstract
    A four channel, self-calibrating, High Resolution Time to Digital Converter (HRTDC) with an RMS error of 35 ps over a dynamic range of 3.2 μs has been developed. Its architecture is based on an array of delay locked loops and an 8-bit coarse time counter driven by an 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read-out FIFO. The HRTDC has been built in a 0.7 μm CMOS process using 23 mm2 of silicon area
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; delay lock loops; nuclear electronics; time measurement; 0.7 micron; 80 MHz; CMOS process; DLL array; coarse time counter; deep read-out FIFO; delay locked loops; four-channel time to digital converter; high-resolution time to digital converter; self-calibrating converter; time registers; Buffer storage; Clocks; Counting circuits; Delay effects; Detectors; Dynamic range; Energy resolution; Time measurement; Timing; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 1998 IEEE International Conference on
  • Conference_Location
    Lisboa
  • Print_ISBN
    0-7803-5008-1
  • Type

    conf

  • DOI
    10.1109/ICECS.1998.813351
  • Filename
    813351
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3430726