Title :
Implementation of ANN on RISC processor array
Author :
Hiraiwa, Atsunobu ; Fujita, Masahiro ; Kurosu, Shigeru ; Arisawa, Shigeru ; Inoue, Makoto
Author_Institution :
Sony Corp. Res. Lab., Kanagawa, Japan
Abstract :
The authors present a mesh systolic array, GCN (giga connection), for a fast simulator of artificial neural networks (ANNs). The processor element (PE) of the GCN is composed of the RISC processor i-860 designed by Intel Corp., a large scale local memory, and high bandwidth first-in first-out devices. The mapping algorithm of the ANN onto the GCN, called the net-data partition, is discussed, and the multilayer feedforward network and Kohenen feature map are mapped onto the GCN by using this algorithm. Another parallelism that can be used for a stochastic ANN like the Boltzmann machine is also discussed. The performance of the GCN is evaluated by software simulation and the authors achieve over 1 gigaconnection per second using 128 PEs
Keywords :
digital simulation; neural nets; reduced instruction set computing; systolic arrays; Boltzmann machine; Kohenen feature map; RISC processor array; artificial neural networks; first-in first-out devices; giga connection; i-860 processor; large scale local memory; mesh systolic array; multilayer feedforward network; net-data partition; software simulation; Artificial neural networks; Bandwidth; Large-scale systems; Multi-layer neural network; Partitioning algorithms; Process design; Reduced instruction set computing; Software performance; Stochastic processes; Systolic arrays;
Conference_Titel :
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-9089-5
DOI :
10.1109/ASAP.1990.145502