Title :
RTL design validation, DFT and test pattern generation for high defects coverage
Author :
Santos, M.B. ; Gonqalves, F.M. ; Teixeira, I.C. ; Teixeira, J.P.
Author_Institution :
IST / INESC-id
Keywords :
Arithmetic; Circuit faults; Circuit testing; Design for testability; Design methodology; Hardware design languages; Power system modeling; System testing; System-on-a-chip; Test pattern generators;
Conference_Titel :
Test Workshop, 2001. IEEE European
Print_ISBN :
0-7695-1017-5
DOI :
10.1109/ETW.2001.946672
