DocumentCode
3430914
Title
Two-level pipelined implementation of systolic block Householder transformation with application to RLS algorithm
Author
Liu, K.J.R. ; Yao, Kai
Author_Institution
Dept. of Electr. Eng., Maryland Univ., College Park, MD
fYear
1990
fDate
5-7 Sep 1990
Firstpage
758
Lastpage
769
Abstract
The authors propose a systolic block Householder transformation (SBHT) approach to implement the Householder transformation (HT) on a systolic array as well as its application to the recursive-least-squares (RLS) algorithm. Since the data are fetched in a block manner, vector operations are in general required for the vectorized array. However, by using a modified HT algorithm, a two-level pipelined implementation can be used to pipeline the SBHT systolic array both at the vector and word levels. The throughput can be as fast as that of the Givens rotation method. The approach makes the HT amenable for VLSI implementation as well as applicable to real-time high throughput applications of modern signal processing. The constrained RLS problem using the SBHT RLS systolic array is also considered
Keywords
VLSI; computerised signal processing; least squares approximations; pipeline processing; systolic arrays; RLS algorithm; VLSI implementation; real-time high throughput applications; recursive-least-squares; signal processing; systolic block Householder transformation; two-level pipelined implementation; vector level; vector operations; word levels; Adaptive signal processing; Array signal processing; Bandwidth; Computer architecture; Resonance light scattering; Signal processing algorithms; Systems engineering and theory; Systolic arrays; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Application Specific Array Processors, 1990. Proceedings of the International Conference on
Conference_Location
Princeton, NJ
Print_ISBN
0-8186-9089-5
Type
conf
DOI
10.1109/ASAP.1990.145510
Filename
145510
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