DocumentCode
3431103
Title
Shallow multiplication circuits
Author
Paterson, Michael S. ; Zwick, Uri
Author_Institution
Warwick Univ., Coventry, UK
fYear
1991
fDate
26-28 Jun 1991
Firstpage
28
Lastpage
34
Abstract
Y. Ofman (1963), C.S. Wallace (1964), and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of two numbers multiplied. An extension of their work is presented. A general theory is presented describing the optimal way in which given carry save adders can be combined into carry save networks. Two new designs of basic carry save adders are described. Using these building blocks and the general theory, the shallowest known theoretical circuits for multiplication are obtained
Keywords
adders; carry logic; digital arithmetic; multiplying circuits; number theory; carry save adders; carry save networks; shallow multiplication circuits; total delay; Adders; Circuits; Computational complexity; Computer science; Contracts; Delay effects; Joining processes; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Arithmetic, 1991. Proceedings., 10th IEEE Symposium on
Conference_Location
Grenoble
Print_ISBN
0-8186-9151-4
Type
conf
DOI
10.1109/ARITH.1991.145530
Filename
145530
Link To Document