A Parallel Architecture for Sampling Rate Conversion Based on Pseudo-DFT

Author

Yuan, Qiang ; Huang, Yuanling ; Yu, Jiangtao

Author_Institution

Southwest Electron. & Telecommun. Technol. Res. Inst., Chengdu

fYear

2008

fDate

12-14 Oct. 2008

Firstpage

1

Lastpage

4

Abstract

A parallel processing architecture for sampling rate conversion in all-digital receiver is proposed in this paper. According to the time shifting property of the FT, the DFT of the desired output samples can be evaluated by the input samples. And the DFT-like transform in this constructed expression can be fast computed by the famous butterfly structure. To overcome the inherent saddle error of this approach, an overlapping input signal strategy is given.

Keywords

discrete Fourier transforms; parallel architectures; radio receivers; sampling methods; all-digital receiver; butterfly structure; inherent saddle error; overlapping input signal strategy; parallel processing architecture; pseudoDFT; sampling rate conversion; time shifting property; Baseband; Clocks; Discrete Fourier transforms; Discrete transforms; Frequency synchronization; Parallel architectures; Parallel processing; Sampling methods; Signal processing; Signal sampling;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2008. WiCOM '08. 4th International Conference on

Conference_Location

Dalian

Print_ISBN

978-1-4244-2107-7

Electronic_ISBN

978-1-4244-2108-4

Type

conf

DOI

10.1109/WiCom.2008.342

Filename

4678251