Process integration technologies for a 0.3 μm BiCMOS SRAM with 1.5 V operation

Author

Suzuki, Hisamitsu ; Yoshida, Hiroshi ; Yamazaki, Tohru ; Takeda, Kohichi ; Kuhara, Shigeru ; Toyoshima, Hideo

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

29 Sep-1 Oct 1996

Firstpage

89

Lastpage

92

Abstract

This paper describes the process integration technologies for low voltage BiCMOS SRAM operation, including a low collector resistance process, a high energy ion implanted p-type isolation, a symmetrical cell layout design and an optimized gate oxide thickness for a boost circuit. These technologies were successfully implemented using 0.3 μm BiCMOS devices where an address access time of 6 ns was demonstrated at 1.5 V for a 4 Mb BiCMOS SRAM

Keywords

BiCMOS memory circuits; SRAM chips; integrated circuit technology; ion implantation; isolation technology; 0.3 micron; 1.5 V; 4 Mbit; 6 ns; BiCMOS SRAM; boost circuit; high energy ion implantation; ion implanted p-type isolation; low collector resistance process; low voltage operation; optimized gate oxide thickness; process integration technologies; symmetrical cell layout design; BiCMOS integrated circuits; Bipolar transistors; Boron; Immune system; Isolation technology; Laboratories; Low voltage; MOSFET circuits; National electric code; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1996., Proceedings of the 1996

Conference_Location

Minneapolis, MN

ISSN

1088-9299

Print_ISBN

0-7803-3516-3

Type

conf

DOI

10.1109/BIPOL.1996.554146

Filename

554146