Design of robust packet synchronization using standard VLSI input-output devices in packet radio communication

A robust packet synchronization technique is analyzed for serial data links which are to be implemented using standard VLSI synchronous input/output (SIO) hardware devices with a built-in 8-bit synchronization correlator. The technique uses a multiple byte marker synchronization in noisy radio channels where forward error correction (FEC) with automatic-repeat-request (ARQ) is used. A tradeoff between reliability and efficiency can be obtained by maximizing the throughput defined as the ratio of the average number of information bits decoded by a decoder to users per unit time to the total number of bits transmitted per unit time. The design parameters, such as code selection and the length of the preamble with respect to the channel error rate are determined for these requirements