A state machine synthesizer with Weinberger arrays

The authors describe the development of a digital circuit synthesis program. The program accepts the transition table of a state machine and returns equations for an implementation that assume a sum-of-product next-state and output functions. From the equations for the next-state and output functions, an nMOS VLSI layout for a Weinberger array (WA) is generated. D-flip-flops are assumed for memory elements. Using this tool, tedious manual calculations can be avoided and layouts are generated automatically from state table descriptions