An intelligent EPROM silicon compiler

Author

Amin, Alaaeldin ; Aref, Mostafa

Author_Institution

Coll. of Comput. Sci. & Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

fYear

1991

fDate

9-10 May 1991

Firstpage

757

Abstract

The authors describe an intelligent EPROM silicon compiler. The compiler accepts high-level specifications of the required EPROM design together with technology and process information and produces CMOS mask geometries for all layers. A knowledge-based kernel determines the chip architecture and required circuit blocks and calls appropriate module generators for each block. Routing algorithms are then used to connect these blocks into a full chip

Keywords

CMOS integrated circuits; EPROM; circuit layout CAD; knowledge based systems; CMOS mask geometries; chip architecture; circuit blocks; high-level specifications; intelligent EPROM silicon compiler; knowledge-based kernel; module generators; routing algorithms; CMOS technology; Circuit testing; EPROM; Kernel; Logic programming; Process design; Programmable logic arrays; Routing; Silicon compiler; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1991., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-87942-638-1

Type

conf

DOI

10.1109/PACRIM.1991.160850

Filename

160850

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3431292