A family of ASIC devices for next generation distributed packet switches with QoS support for IP and ATM

Author

Chiussi, Fabio M. ; Brizio, Alberto ; Francini, Andrea ; Grant, Kevin ; Kazi, Khurram ; Khotimsky, Denis ; Krishnan, Santosh ; Shen, Sheng ; Syed, Mohammad ; Wasilewski, Thomas

Author_Institution

Data Networking Syst. Res. Dept., Lucent Technol. Bell. Labs., Holmdel, NJ, USA

fYear

2001

fDate

2001

Firstpage

145

Lastpage

149

Abstract

The protocol-independent (π) family of ASIC devices, which we present in this paper, allows to build cost-effective IP routers and ATM switches capable of providing sophisticated Quality-of-Service (QoS) guarantees in the form of throughput, delay and jitter to individual flows or to aggregation of flows. The new chipset, which represents the evolution of the widely used ATLANTA chipset, comprises five devices. The devices presented considerable design and verification challenges, due to the complexity and required speed of the desired QoS functionality. To solve these challenges, we devised a number of design techniques, as well as a novel ad-hoc verification approach

Keywords

application specific integrated circuits; asynchronous transfer mode; computational complexity; jitter; packet switching; quality of service; ASIC devices; ATLANTA chipset; ATM; ATM switches; IP; IP routers; QoS support; ad-hoc verification approach; complexity; delay; jitter; next generation distributed packet switches; protocol-independent family; quality-of-service; throughput; Application specific integrated circuits; Asynchronous transfer mode; Fabrics; Jitter; Packet switching; Scheduling; Switches; Telecommunication traffic; Throughput; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Hot Interconnects 9, 2001.

Conference_Location

Stanford, CA

Print_ISBN

0-7695-1357-3

Type

conf

DOI

10.1109/HIS.2001.946707

Filename

946707