CMOS scaling towards its limits

Author

Iwai, Hiroshi

Author_Institution

Toshiba Corp., Japan

fYear

1998

fDate

1998

Firstpage

31

Lastpage

34

Abstract

CMOS LSIs are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, CMOS scaling towards its limits are explained based on the experimental results of the downsizing MOSFET into such dimension, and further concept for deep-sub-0.1 μm CMOS is described

Keywords

CMOS integrated circuits; MOSFET; VLSI; integrated circuit technology; large scale integration; nanotechnology; 0.1 micron; CMOS LSI; CMOS scaling; MOSFET downsizing; deep submicron technology; deep-sub-0.1 μm; minimum feature size; CMOS technology; Digital circuits; Economic forecasting; Humans; Large Hadron Collider; Large scale integration; MOSFETs; Random access memory; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785777

Filename

785777