Low power consumption communication systems

The authors reduced power consumption by considering the system at all levels of design. In the area of overall implementation, the authors reduced the chip-to-chip connections by utilizing logic gates with the smallest area and further by using a technique known as high-density interconnect. The interconnection between the dies is done using ultra-fine metal lines drawn with the help of a computer-guided laser. This reduces the capacitative load at each pin by an order of magnitude as compared to conventional techniques. In this technology the chips almost touch one another, thus achieving area densities that can reach 90%. In the area of architecture a switching network was used to increase the computational capability of limited resources. In the area of circuit design, an innovative CMOS technique which reduces power consumption of the gates while at the same time decreasing the delay and size of the circuits was used