Concurrent Optimization of Technology and Design for Nano CMOS

Author

Amerasekera, Ajith

Author_Institution

Texas Instrum.

fYear

2007

fDate

6-10 Jan. 2007

Firstpage

27

Lastpage

27

Abstract

As we move to 45nm and beyond, our ability to manage the need for increased integration together with the drive for higher system performance and lower power presents many challenges to technology and design. It has become no longer possible to consider technology advancement without considering the overall optimization of the transistor and circuit design for full entitlement together with the cost of the chip. This paper looks at the key challenges and technology discontinuities that we face as we move into the nano CMOS regime, and some of the approaches being developed to address them

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; nanotechnology; circuit optimization; concurrent optimization; nano CMOS; Application specific integrated circuits; CMOS technology; Circuit synthesis; Design optimization; Electrostatic discharge; Energy management; Instruments; Power system management; Technology management; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-2762-0

Type

conf

DOI

10.1109/VLSID.2007.51

Filename

4092015