DocumentCode :
3431826
Title :
Reusing Learned Information in SAT-based ATPG
Author :
Fey, Görschwin ; Warode, Tim ; Drechsler, Rolf
Author_Institution :
Inst. of Comput. Sci., Bremen Univ.
fYear :
2007
fDate :
6-10 Jan. 2007
Firstpage :
69
Lastpage :
76
Abstract :
The robustness of engines for ATPG has to be improved to cope with the growing size of circuits. Recently, SAT-based ATPG approaches have been shown to be very robust even on large industrial circuits. Here, we propose techniques to further improve the efficiency by embedding learning techniques in a SAT-based ATPG engine. We provide a heuristic to apply incremental SAT when enumerating faults and a technique to apply circuit-based learning where incremental SAT is not applicable. The correctness of circuit-based learning is proven. Experimental results on large benchmarks show the efficiency
Keywords :
automatic test pattern generation; computability; logic testing; SAT-based ATPG; automatic test pattern generation; circuit-based learning; computability; learning techniques; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Computer science; Databases; Delay; Engines; Redundancy; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
0-7695-2762-0
Type :
conf
DOI :
10.1109/VLSID.2007.137
Filename :
4092025
Link To Document :
بازگشت