FPGA Implementation of Low Power Parallel Multiplier

In the fast growing communication field, requirements of low power designs are increasing to reduce the power losses and decrease the thermal losses in the same ratio. Multiplier is an arithmetic circuit that is extensively used in common DSP and communication applications. This paper presents low power multiplier design methodology that inserts more number of zeros in the multiplicand thereby reducing the number of switching activities as well as power consumption. Use of look up table is an added feature to this design. Modifying the structure of adders further reduces switching activity