DocumentCode
3432106
Title
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Author
Wang, Feng ; Xie, Yuan ; Rajaraman, R. ; Vaidyanathan, B.
Author_Institution
Pennsylvania State Univ., University Park, PA
fYear
2007
fDate
6-10 Jan. 2007
Firstpage
165
Lastpage
170
Abstract
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits
Keywords
MOSFET; combinational circuits; error statistics; integrated circuit modelling; logic testing; radiation effects; semiconductor device models; table lookup; HSPICE simulation; MOSFET models; combinational logic circuits; electrical masking model; pulse propagation model; soft error rate analysis; submicron MOS transistors; table lookup; transient pulse generation model; Circuit simulation; Combinational circuits; Error analysis; Error correction codes; Estimation error; Latches; Logic gates; Pulse generation; Transient analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-7695-2762-0
Type
conf
DOI
10.1109/VLSID.2007.145
Filename
4092040
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