Title :
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design
Author :
Sarkar, Deblina ; Ganguly, Samiran ; Datta, Deepanjan ; Sarab, A.A.P. ; Dasgupta, Sudeb
Author_Institution :
Dept. of Electron. & Instrum. Eng., Indian Sch. of Mines, Dhanbad
Abstract :
Double-gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. In this paper, we investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrodinger simulator with tight-binding Green´s function approach. Then we analyze the effect of parameter variation to optimize low leakage SRAM cell using DG devices. The DG device/circuit co-design successfully demonstrates the benefit of using metal gate intrinsic body DG devices which significantly reduces BTBT and EDT in SRAM architecture
Keywords :
MOSFET; SRAM chips; low-power electronics; semiconductor device models; 10 nm; 2D Poisson-Schrodinger simulator; Green´s function; double-gate MOSFET; gate-to-channel leakage; leakage modeling; logic circuit design; low power SRAM; memory circuit design; nanoscale DG MOSFET; subthreshold leakage; Circuit simulation; Circuit synthesis; Green´s function methods; Logic circuits; Logic design; Logic devices; MOSFET circuits; Nanoscale devices; Power MOSFET; Random access memory;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.110
