Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation

Author

Kumar, Jagadesh M. ; Venkataraman, Vivek ; Nawal, Susheel

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi

fYear

2007

fDate

6-10 Jan. 2007

Firstpage

189

Lastpage

194

Abstract

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations

Keywords

Ge-Si alloys; MOSFET; circuit simulation; elemental semiconductors; semiconductor device models; silicon; 2D device simulations; Si-SiGe; analog circuit simulation; drain current model; nanoscale CMOS applications; nanoscale strained-Si/SiGe MOSFET; short channel devices; strained-silicon devices; velocity overshoot effect; Analog circuits; Analytical models; CMOS process; Capacitive sensors; Circuit simulation; Germanium silicon alloys; MOSFETs; Nanoscale devices; Semiconductor device modeling; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-2762-0

Type

conf

DOI

10.1109/VLSID.2007.38

Filename

4092044