Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective

In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo simulations to analyze the effects of variations of T_ox and V_DDon the statistical distribution of these metrics. We concentrate on 3 different unique quantities: (i) steady-state ON current (I_ON); (ii) Steady-state OFF current (I_OFF); and (iii) effective tunneling capacitance during transitions (C_eff ^t). We define C_eff ^t as the change in tunneling current with respect to the rate of change of input voltage, which represents the capacitive load of the transistor due to tunneling. It concisely encapsulates information about the swing in tunneling current during state transitions while simultaneously accounting for the transition rate. We demonstrate that the effect can be very significant due to the exponential dependence of the metrics on process parameters and this dependence also translates into a lognormal distribution for the metrics themselves. We first consider NMOS and PMOS devices individually and subsequently their interaction in an inverter