Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis

High-performance circuit optimization and synthesis should consider parasitic effects. This paper introduces techniques for parasitic estimation and fast parasitic optimization based on symbolic sensitivity analysis. An effective framework to incorporate parasitic modeling and optimization is presented in order to account for parasitic effects during synthesis. In this paper we primarily focus on using efficient symbolic sensitivity analysis based on element-coefficient diagrams (ECD) to evaluate the dominant parasitic effects so as to eliminate insignificant parasitics. An ECD is the cancellation-free and per-coefficient term generation version of determinant decision diagrams (DDDs). In this paper, parasitic-aware analog circuit synthesis methodology is proposed. The accuracy and efficiency of the parasitic-inclusive optimization have been demonstrated