Title :
Modeling and Analysis of Noise Margin in SET Logic
Author :
Sathe, Chaitanya ; Mahapatra, Santanu
Author_Institution :
C.E.D.T, Indian Inst. of Sci., Bangalore
Abstract :
In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model. The variation of the noise margin with temperature and background charge is also studied. A chain of SET inverters is simulated to validate the definition of various logic levels (like VIH, VOH, etc.) and noise margin. Finally the noise immunity of SET logic is compared with current CMOS logic
Keywords :
invertors; logic circuits; semiconductor device models; single electron transistors; Mahapatra-Ionescu-Banerjee model; SET inverters; SET logic; background charge; logic levels; noise immunity; single electron transistor logic; static noise margin; temperature charge; Background noise; CMOS logic circuits; CMOS process; Capacitance; Conductors; MOSFET circuits; Pulse inverters; Single electron transistors; Temperature; Tunneling;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.109
