Customization of Register File Banking Architecture for Low Power

Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application specific customization of register file banking structure. First, we propose two techniques based on: (i) profiling; and (ii) static application analysis to arrive at a customized energy-efficient bank configuration for a given application on a dual bank register file. We also propose a technique to extend the exploration to a multi-bank register file architecture and an associated register allocation algorithm for further power reduction. This reduces register file power consumption by allocating variables in frequently accessed basic blocks to separate appropriately sized register file bank of active registers. Experimental results indicate that our customized dual bank configuration inferred by both techniques gives energy savings of 40% over a monolithic register file, and the multi-bank register file customization gives a further 15-20% energy savings