A Novel CMOS Full Adder

Author

Navi, Keivan ; Kavehie, Omid ; Rouholamini, Mahnoush ; Sahafi, Amir ; Mehrabi, Shima

Author_Institution

Dept. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran

fYear

2007

fDate

Jan. 2007

Firstpage

303

Lastpage

307

Abstract

This paper proposes a high-speed adder cell using a new design style called "bridge". The bridge design style offers more regularity and higher density than conventional CMOS design style, by using some transistors, named bridge transistors. Results show 4.4% (@ Vdd=3 volt) to 34.1% (@ Vdd=1 volt) improvement in speed over conventional CMOS adder. HSPICE is the circuit simulator used, and the technology being used for simulations is BSIM3v3 0.18mum technology

Keywords

CMOS logic circuits; SPICE; circuit simulation; high-speed integrated circuits; integrated circuit design; 0.18 micron; 1 V; 3 V; BSIM3v3; CMOS design style; CMOS full adder; HSPICE; bridge design style; bridge transistors; circuit simulator; high-speed adder cell; Adders; Arithmetic; Bridge circuits; CMOS logic circuits; CMOS technology; Circuit simulation; Design engineering; Energy consumption; MOS devices; Robust stability;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-2762-0

Type

conf

DOI

10.1109/VLSID.2007.18

Filename

4092062

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3432516