DocumentCode :
3432789
Title :
Detection and Generation of Self-Timed Pipelines from High Level Specifications
Author :
Cheng, Fu-Chiung ; Chang, Shu-Ming ; Shieh, Chi-Huam
Author_Institution :
Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei
fYear :
2007
fDate :
6-10 Jan. 2007
Firstpage :
413
Lastpage :
418
Abstract :
System level design is becoming the major design methodology for system-on-a-chip (SOC) design with IP (intellectual property) reuse to solve the productivity gap problem. How to synthesis efficient hardware from high level specifications, such as Java, SystemC or C++, is becoming an important issue. This paper presents a novel methodology to extract pipeline stages from high level behavioral models to improve performance. A set of self-timed pipeline modules is designed and implemented for constructing these pipeline stages. The preliminary experimental result shows that, when the summation/modular multiplication is partitioned into two pipelined stages, the pipelined summation/modular multiplication is 1.94/1.61 times faster than the non-pipelined version with 15.8%/´1.8% hardware overhead
Keywords :
asynchronous circuits; high level synthesis; logic partitioning; system-on-chip; C++; Java; SystemC; high level behavioral models; high level specifications; intellectual property reuse; pipeline stages; self-timed pipelines; summation/modular multiplication; system level design; system-on-a-chip design; Asynchronous circuits; Design automation; Design methodology; Hardware; Hazards; Java; Pipeline processing; Productivity; System-level design; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
0-7695-2762-0
Type :
conf
DOI :
10.1109/VLSID.2007.66
Filename :
4092079
Link To Document :
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