Model Based Test Generation for Microprocessor Architecture Validation

Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used in simulation based validation, like simulators and test generators, to validate the system, architecture, microcode, and RTL abstractions of the processor, were manually derived from the specification document. The incomplete informal specification document along with manual translation introduces inconsistency and bugs in the validation collaterals, resulting in increased cost and time to validate the processor. We envision a novel metamodeling based microprocessor modeling and validation environment (MMV) to address this problem. MMV provides a language independent modeling environment to describe the processor at various abstraction levels, a refinement flow to consistently move from one abstraction to the next lower abstraction and code generators to automatically generate the validation collaterals from the models. As a first step towards our vision, in this paper, we describe architectural modeling in MMV and automatic generation of random and coverage directed test suites from the models. We demonstrate the practicality of our approach for validating real world instruction set architectures (ISA) by modeling and generating test cases for eight complex instructions from Intel¹ reg virtualization technology