• DocumentCode
    3432972
  • Title

    Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)

  • Author

    Rahaman, H. ; Mathew, J. ; Pradhan, D.K.

  • Author_Institution
    Dept. of Comput. Sci., Bristol Univ.
  • fYear
    2007
  • fDate
    6-10 Jan. 2007
  • Firstpage
    479
  • Lastpage
    484
  • Abstract
    In this paper, a C-testable implementation of polynomial basis (PB) bit parallel (BP) multiplier over the Galois fields of form GF(2 m) for detecting stuck-at faults in multiplier circuits has been proposed. The length of the constant test set is only 8. The fault detection can be incorporated in the multiplier circuit with only three extra inputs for controllability. The gate counts of the proposed testable multiplier as a function of degree m is also analyzed. The proposed constant test set is much smaller than ATPG generated or algorithmic test set, resulting in low power testability. As the GF(2 m) multipliers have found some critical field applications and need for efficient online testing, built-in self-test (BIST) circuit is proposed to generate test pattern internally. This BIST also obviates the need of having three extra pins for the control inputs. Area and delay of testable circuits and BIST circuit is analyzed using 0.18mum CMOS technology library from UMC. The proposed test pattern has the intrinsic ability to detect single bit errors in the test pattern generator (TPG) itself. The test set provides 100 percent single fault coverage
  • Keywords
    CMOS logic circuits; Galois fields; automatic test pattern generation; built-in self test; digital arithmetic; fault diagnosis; logic testing; multiplying circuits; 0.18 micron; BIST circuit; CMOS technology; Galois fields; bit parallel multipliers; built-in self-test; constant function independent test set; efficient online testing; error control code; intrinsic ability; low power testability; multiplier circuits; polynomial basis multiplier; single fault coverage; stuck-at faults detection; test pattern generation; testable circuits; Automatic testing; Built-in self-test; CMOS technology; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Galois fields; Polynomials; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2762-0
  • Type

    conf

  • DOI
    10.1109/VLSID.2007.53
  • Filename
    4092089