Characterization and modeling of MOSFET mismatch of a deep submicron technology

Author

Quarantelli, Michele ; Saxena, Sharad ; Dragone, Nicola ; Babcock, Jeff A. ; Hess, Christopher ; Minehane, Seán ; Winters, Steve ; Chen, Jianjun ; Karbasi, Hossein ; Guardiani, Carlo

Author_Institution

PDF Solutions, San Jose, CA, USA

fYear

2003

fDate

17-20 March 2003

Firstpage

238

Lastpage

243

Abstract

CMOS technology scaling increases the sensitivity of many common circuit blocks to within die variation and local mismatch. Accurate assessment of the impact of mismatch on these circuits requires extremely precise estimates of mismatch. This paper analyzes the inaccuracies that occur in mismatch estimation methods that rely on combining measurements from a different die and wafers. Use of device arrays to overcome this limitation is described. Measurements from device arrays on a 0.13 μm CMOS technology suggest that for technologies with good control of device dimensions, 1/sqrt(WL) relationship of mismatch holds over a very large range of device dimensions.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit measurement; integrated circuit modelling; parameter estimation; 0.13 micron; CMOS technology scaling; MOSFET mismatch; circuit block sensitivity; deep submicron technology; device arrays; device dimensions control; local mismatch; mismatch estimates; mismatch estimation method limitations; modeling; within die variation; Analog circuits; CMOS technology; Circuit noise; Circuit testing; Digital-analog conversion; Intrusion detection; MOSFET circuits; Sampling methods; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2003. International Conference on

Print_ISBN

0-7803-7653-6

Type

conf

DOI

10.1109/ICMTS.2003.1197468

Filename

1197468