Characterization and modeling of MOSFET mismatch of a deep submicron technology

CMOS technology scaling increases the sensitivity of many common circuit blocks to within die variation and local mismatch. Accurate assessment of the impact of mismatch on these circuits requires extremely precise estimates of mismatch. This paper analyzes the inaccuracies that occur in mismatch estimation methods that rely on combining measurements from a different die and wafers. Use of device arrays to overcome this limitation is described. Measurements from device arrays on a 0.13 μm CMOS technology suggest that for technologies with good control of device dimensions, 1/sqrt(WL) relationship of mismatch holds over a very large range of device dimensions.