• DocumentCode
    3433077
  • Title

    JouleQuest: An Accurate Power Model for the StarCore DSP Platform

  • Author

    Mathur, Ashish ; Roy, Sourav ; Bhatia, Rajat ; Chakraborty, Arup ; Bhargava, Vijay ; Bhartia, Jatin

  • Author_Institution
    India Design Center, Freescale Semicond., Noida
  • fYear
    2007
  • fDate
    6-10 Jan. 2007
  • Firstpage
    521
  • Lastpage
    526
  • Abstract
    This paper describes the design, validation and integration of JouleQuest: a comprehensive power estimation framework for the StarCore DSP platform. The goal of this work is to provide a power model coupled to a fast platform simulator, that can accurately predict the power variability on the platform. The power consumption model for the DSP core is an instruction level model while the power models for the peripheral components are based on functional operations executed by the blocks. The DSP core instruction level power model is a generic model applicable to any VLIW DSP core and improves on existing VLIW models by reducing the model complexity to O(n) where n is the number of processor instructions. The peripheral power models are based on a novel technique of characterizing the power of operations and operation sequences executed on the peripheral block. This allows accurate power modeling for complex peripheral blocks like cache controllers, arbiters etc. having significant parallel operation execution. The platform power has been verified to give an average error of approximately 5% across a large suite of DSP and control benchmarks having high power variability. The paper concludes with a case study demonstrating the usage of the power simulator for energy optimization of ITU-T G.729 speech-codec software
  • Keywords
    digital signal processing chips; instruction sets; ITU-T G.729 speech-codec; JouleQuest; StarCore DSP; VLIW DSP core; cache controllers; energy optimization; instruction level; peripheral components; power estimation; power variability; Analytical models; Application software; Circuits; Computer architecture; Digital signal processing; Energy consumption; Optimizing compilers; Power system modeling; Predictive models; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2762-0
  • Type

    conf

  • DOI
    10.1109/VLSID.2007.95
  • Filename
    4092095