An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect

With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 25% of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called the loading effect. In this paper, the authors propose a pattern dependent steady state leakage estimation technique that incorporates loading effect and accounts for all three major leakage components, namely the gate, band to band tunneling and sub-threshold leakage and accounts for transistor stack effect. The proposed estimation technique has been validated against SPICE and can be deployed on larger circuits where SPICE simulation is infeasible. In this paper, we report a speed up of 2,000-70,000times speed-up over SPICE simulation on smaller circuits, where spice simulation is feasible. Further results show that loading effect is a significant factor in leakage that worsens with technology scaling