FPGA optimised 3-D cyclic convolution using dynamic partial reconfiguration

This paper presents the design and implementation of a generic three-dimension (3-D) cyclic convolution (CC) on field programmable gate array (FPGA). Three CC calculation architectures have been proposed and integrated into the 3-D framework. Architectures using FPGA specific digital signal processor (DSP) and distributed arithmetic (DA) cores have been implemented on Xilinx Virtex-5 FPGAs. Experimental results and performance analysis of the area, power consumption, maximum frequency and throughput are covered in this paper. Finally, an evaluation of the generic CC has been carried out and reveals a significant trade-off of throughput and maximum frequency, whilst the DA implementation exhibits the reduction size of the read only memory (ROM) to store the precomputed values.