Evaluating the performance of a configurable, extensible VLIW processor in FFT execution

This paper presents the setup and the evaluation of the LE1 configurable, extensible, multi-cluster VLIW processor system in FFT execution. The input code is a C implementation of the FFT algorithm and we evaluate its performance on the LE1 simulator for multiple CPU configurations (issue width, execution resource mix, custom instruction) and compiler optimizations (inlining, loop unrolling) in an effort to optimize the cycle count. We identify the prevailing LE1 configurations, with respect to the FFT cycle performance, their silicon area and the power dissipation. Finally, we compare these results to a fully systolic single datapath delay feedback (SDF) VLSI FFT architecture derived from the same C code.