• DocumentCode
    3433439
  • Title

    A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

  • Author

    Joshi, Rajiv V. ; Kim, Keunwoo ; Williams, Richard Q. ; Nowak, Edward J. ; Chuang, Ching-Te

  • Author_Institution
    IBM T. J. Watson Res. Center, Yorktown Heights, NY
  • fYear
    2007
  • fDate
    6-10 Jan. 2007
  • Firstpage
    665
  • Lastpage
    672
  • Abstract
    This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n+/p+ polysilicon gates) FinFETs devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below-GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the read/write performance, reduce standby leakage, and mitigate process (VT) variability. The application of the technique to stacked read transistors in 8-T SRAM is also discussed.
  • Keywords
    MOSFET; SRAM chips; 6-T SRAM; 8-T SRAM; FinFET technology; independent-gate control; mitigate process variability; pull-down cell nFET; read/write performance; stable SRAM row-based back-gate biasing scheme; standby leakage reduction; static random-access storage; CMOS logic circuits; Costs; Diodes; FinFETs; Fluctuations; Frequency; Logic devices; Random access memory; Tunneling; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2762-0
  • Type

    conf

  • DOI
    10.1109/VLSID.2007.182
  • Filename
    4092118
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3433439