Layout exploration of geometrically accurate arithmetic circuits

High-performance arithmetic circuits are critical to overall design performance and are therefore designed using full-custom design techniques. However, this is a time-consuming and error-prone task. We present a novel layout exploration methodology to design arithmetic circuits using standard-cell techniques, that retains competitive performance while allowing an almost custom-design kind of control over the layout. It uses an unconventional approach with a Haskell-based front-end in the Wired system, designed to produce logically and topologically accurate circuit descriptions and at the same time be parameterizable. Further, another overall goal of the system was to keep implementation time as low as possible. We demonstrate this methodology on HPM multipliers that exhibit a high degree of layout regularity.