Consideration of the structure design for thin SOI/MOSFET under and beyond the half micron regime

A salicide process for thin SIMOX MOSFETs was developed, and the prospect of device application in the submicron regime was examined by evaluating the current drivability of MOSFETs and analyzing its limiting factors in both short and long channel regions. One problem in the scaling of thin-SOI MOSFETs (especially for NMOS) was the lowered drain breakdown voltage caused by parasitic bipolar operation due to a floating body structure. Latch-up phenomena in a unit NMOS diminishes the reliable operation of the CMOS circuit. The problem can be solved by lowering the drain electric field to reduce generated holes from impact ionization which reinforces parasitic bipolar operation. The authors studied the LDD (lightly doped drain) structure and an advanced gate overlapped LDD structure for device application of the thin-SOI/MOSFET under and beyond the half-micron regime