DocumentCode :
3433744
Title :
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n)
Author :
Sudhakar, M. ; Kamala, R.V. ; Srinivas, M.B.
Author_Institution :
Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad
fYear :
2007
fDate :
Jan. 2007
Firstpage :
750
Lastpage :
755
Abstract :
This paper proposes a unified and reconfigurable Montgomery multiplier architecture which can operate in both primary GF(p) and binary extension fields GF(2^n). The multiplier provides efficient execution of Montgomery multiplication in either field for different operand lengths. It supports any operand length ´n´, 1le n le N where the upper value of N is application dependent. The final result is obtained in ´n+2´ clock cycles for either field. Propagation delay of the design is investigated and found to be comparable with the existing unified multiplier architectures while providing reconfigurability at the same time. The proposed architecture has high order of flexibility and low hardware complexity with critical path delay independent of operand length. The multiplier can find application in, for example, Elliptic curve cryptographic(ECC) processors.
Keywords :
Galois fields; multiplying circuits; Galois fields; Montgomery multiplication; elliptic curve cryptographic processors; finite fields; n+2 clock cycles; propagation delay; reconfigurable architecture; unified multiplier architectures; Clocks; Computer architecture; Delay; Elliptic curve cryptography; Embedded system; Galois fields; Hardware; Information technology; Reconfigurable architectures; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore, India
ISSN :
1063-9667
Print_ISBN :
0-7695-2762-0
Type :
conf
DOI :
10.1109/VLSID.2007.27
Filename :
4092131
Link To Document :
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