DocumentCode :
3433764
Title :
A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems
Author :
Han, J.H. ; Erdogan, A.T. ; Arslan, T.
Author_Institution :
Edinburgh Univ.
fYear :
2007
fDate :
Jan. 2007
Firstpage :
756
Lastpage :
762
Abstract :
A maximum likelihood detector (MLD) is presented for 4times4 QPSK multiple-input multiple-output (MIMO) systems. A hybrid methodology combining precomputation of norm values followed with the transformation of the maximum likelihood algorithm is applied in order to achieve an efficient MLD implementation, in which 16 norm values are concurrently computed for high throughput while maintaining power and area efficiency. The MLD implementation results are compared with a conventional MLD in area and power. Simulation results demonstrate that the proposed MLD can achieve up to 74 Mbps throughput at a clock speed of 147MHz
Keywords :
MIMO communication; logic circuits; maximum likelihood decoding; maximum likelihood estimation; quadrature phase shift keying; 147 MHz; 74 Mbits/s; MIMO systems; QPSK; maximum likelihood detector; multiple-input multiple-output; AWGN; Bit error rate; Clocks; Concurrent computing; Detectors; MIMO; Maximum likelihood detection; Quadrature phase shift keying; Receiving antennas; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
0-7695-2762-0
Type :
conf
DOI :
10.1109/VLSID.2007.22
Filename :
4092132
Link To Document :
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