An improved comparison circuit for low power pre-computation-based content-addressable memory designs

This paper proposes a CMOS comparison architecture for low-power pre-computation-based content-addressable memory (PB-CAM). Instead of conventional architecture, we implement ours by CMOS logic gates to eliminate power consumption induced by short-circuit current. We use TSMC 0.18-¿m techfile to estimate the power consumption by Synopsys Nanosim. The width ratio between PMOS and NMOS is set as 3:1. This ratio can effectively reduce both rise time and fall time, thereby reducing the delay for each comparison cycle. Compare with static pseudo-nMOS CAM word circuit, this architecture can save 50.2% power consumption on average.