DocumentCode
3434
Title
Low Latency Systolic Montgomery Multiplier for Finite Field
Based on Pentanomials
Author
Jiafeng Xie ; Jian jun He ; Meher, Pramod Kumar
Author_Institution
Sch. of Inf. Sci. & Eng., Central South Univ., Changsha, China
Volume
21
Issue
2
fYear
2013
fDate
Feb. 2013
Firstpage
385
Lastpage
389
Abstract
In this paper, we present a low latency systolic Montgomery multiplier over GF(2m) based on irreducible pentanomials. An efficient algorithm is presented to decompose the multiplication into a number of independent units to facilitate parallel processing. Besides, a novel so-called “pre-computed addition” technique is introduced to further reduce the latency. The proposed design involves significantly less area-delay and power-delay complexities compared with the best of the existing designs. It has the same or shorter critical-path and involves nearly one-fourth of the latency of the other in case of the National Institute of Standards and Technology recommended irreducible pentanomials.
Keywords
Galois fields; critical path analysis; multiplying circuits; parallel processing; systolic arrays; National Institute of Standards and Technology; area-delay; critical-path; finite field GF(2m); independent units; irreducible pentanomials; latency reduction; low latency systolic montgomery multiplier; multiplication decomposition; parallel processing; power-delay complexity; pre-computed addition; Arrays; Delay; Logic gates; NIST; Polynomials; Principal component analysis; Very large scale integration; Low latency; Montgomery multiplication; pentanomials; systolic structure;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2012.2185257
Filename
6144735
Link To Document