DocumentCode :
3434074
Title :
Application of DC Analyzer to Combinatorial Optimization Problems
Author :
Trivedi, Gaurav ; Punglia, Sumit ; Narayanan, H.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai
fYear :
2007
fDate :
6-10 Jan. 2007
Firstpage :
869
Lastpage :
874
Abstract :
Solution of many combinatorial optimization problems can be found by analyzing appropriate electrical networks made up of positive resistors, voltage sources, current sources and ideal diodes. This method is an alternative approach for the approximate solution of such problems. Two graph method based fast simulator is a more suitable option for this purpose than modified nodal analysis based conventional simulators. Using this approach the authors have made an attempt to solve min cost flow and single source shortest path problems. A planar min cost flow problem of size 200,000 nodes and 600,000 edges is solved by our simulator approximately within 0.1% of the optimum solution in about 11 mins. The authors have exactly solved a planar single source shortest path problem (having negative edge weights also) of size 100, 000 nodes and 600, 000 edges in about 2 mins. The authors have performed our experiments on a PIV processor having 1 GB RAM
Keywords :
circuit optimisation; microprocessor chips; network analysis; random-access storage; 1 Gbit; DC analyzer; PIV processor; RAM; combinatorial optimization problems; electrical networks; two graph method; Analytical models; Circuits; Cost function; Diodes; Iterative methods; Resistors; Shortest path problem; Symmetric matrices; Transmission line matrix methods; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
0-7695-2762-0
Type :
conf
DOI :
10.1109/VLSID.2007.39
Filename :
4092150
Link To Document :
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