Title :
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Author :
Sinha, Debjit ; Luo, Jianfeng ; Rajagopalan, Subramanian ; Batterywala, Shabbir ; Shenoy, Narendra V. ; Zhou, Hai
Abstract :
This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant
Keywords :
chemical mechanical polishing; dielectric materials; integrated circuit interconnections; 3D field solvers; chemical mechanical polishing; dummy fills; electrical parameters; interconnects; modern process technology; multiple thin inter-layer dielectrics; trapezoidal conductor cross-sections; Aluminum; Conductors; Copper; Dielectrics; Etching; Integrated circuit interconnections; Manufacturing processes; Parasitic capacitance; Planarization; Timing;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.90
