Title :
Salicide technology for fully-depleted SOI CMOS devices
Author :
Gallegos, R. ; Sullivan, M.
Author_Institution :
United Technol. Microelectron. Center, Colorado Springs, CO, USA
Abstract :
Self-aligned silicide (salicide) is necessary to reduce device resistances associated with an ultra-thin film fully-depleted (UTF/FD) CMOS SOI technology. A salicide process for use with UTF/FD CMOS SOI devices is developed, and subsequent transistor characteristics are shown. Process optimization was achieved through experimental design techniques by minimizing salicide sheet resistance and improving salicide uniformity across the wafer. Replicates at the center points of the experimental designs determined the repeatability of the process and the ability of the models to predict responses. The salicide process developed for SOI is a four-step procedure: (1) Ti deposition (500 Å), (2) monosilicide formation (600-700°C), (3) TiN/Ti removal (1:1 NH4OH:H2O2), and (4) disilicide formation (700-800°C)
Keywords :
CMOS integrated circuits; integrated circuit technology; metallisation; semiconductor technology; semiconductor-insulator boundaries; 600 to 700 degC; 700 to 800 degC; Si-SiO2; TiSi2-Si-SiO2; disilicide formation; four-step procedure; fully-depleted SOI CMOS devices; monosilicide formation; process optimisation; salicide process; salicide uniformity; self-aligned silicide; transistor characteristics; Annealing; CMOS process; CMOS technology; Design for experiments; Implants; Silicon on insulator technology; Space technology; Surface resistance; Temperature; Tin;
Conference_Titel :
SOS/SOI Technology Conference, 1990., 1990 IEEE
Conference_Location :
Key West, FL
Print_ISBN :
0-87942-573-3
DOI :
10.1109/SOSSOI.1990.145718