Title :
Process integration of a direct-on-metal, non-etchback, κ=2.5 spin-on polymer for the 0.18 μm CMOS technology node
Author :
Sum, Joyce C. ; Ray, Gary W. ; Ma, Shaming ; Kavari, Rahim ; MacInnes, Lisa M. ; Treadwell, Carl A. ; Dunne, Jude ; Hacker, Nigel P. ; Figge, Lisa K. ; Hendricks, Neil
Author_Institution :
Lab. of ULSI Res., Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
Process integration of a κ=2.5 spin-on dielectric polymer into double-level metal CMOS parametric test structures at two technology nodes (0.35 μm and 0.18 μm) is described. This was accomplished using a single-coat, DOM (direct-on-metal), NEB (nonetchback) process. The structures are globally planarized using a standard CMP process on an oxide-based layer used to cap the low-k spin-on dielectric. Details of the process are presented together with electrical data demonstrating very low capacitance and low leakage current, even after multiple thermal cycles
Keywords :
CMOS integrated circuits; capacitance; chemical mechanical polishing; dielectric thin films; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit testing; leakage currents; permittivity; polymer films; spin coating; 0.18 micron; 0.35 micron; CMOS technology node; capacitance; direct-on-metal nonetchback spin-on polymer; double-level metal CMOS parametric test structures; electrical data; globally planarized structures; leakage current; low-k spin-on dielectric; multiple thermal cycles; oxide-based cap layer; process integration; single-coat DOM NEB process; single-coat direct-on-metal nonetchback process; spin-on dielectric polymer; standard CMP process; technology nodes; CMOS process; CMOS technology; Capacitance; Dielectric materials; Etching; Fabrication; Planarization; Plugs; Polymers; Tin;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787116
