DocumentCode
3434326
Title
Improving quality: yield vs. test coverage (WSI)
Author
Millman, Steven D.
Author_Institution
Motorola Inc., Tempe, AZ, USA
fYear
1993
fDate
1993
Firstpage
279
Lastpage
288
Abstract
It is shown that for typical values of test coverage and yield, increasing the test coverage will have a greater impact on quality for a lower cost than similar increases in yield. This relationship often holds even when the increase in yield is much larger than the increase in test coverage. It must be ensured that the test coverage is based on fault models that accurately describe the behavior of fault chips, and that the simulated faults accurately represent the failures that actually occur.
Keywords
VLSI; electrical faults; failure analysis; integrated circuit technology; integrated circuit testing; quality control; WSI technology; failures; fault chips; fault models; quality; simulated faults; test coverage; yield; Costs; Fault detection; Fault diagnosis; Manufacturing processes; Predictive models; Pulp manufacturing; Semiconductor device modeling; Testing; Virtual manufacturing; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-0867-0
Type
conf
DOI
10.1109/ICWSI.1993.255250
Filename
255250
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